1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to the tracing of program instructions being executed by a data processing circuit.
2. Description of the Prior Art
As data processing systems increase in complexity, it is becoming more important to provide comprehensive and effective mechanisms for analysing the behaviour of such systems, for example, as part of system debugging and the like. Furthermore, as the speed of the data processing systems increases and the number of integrated elements typically contained increases, there is a corresponding increase in the amount of trace data that is generated and the speed at which it is generated.
It is known to provide on-chip trace facilities for data processing systems in which dedicated circuitry is provided upon the integrated circuit for tracing the activity of the circuit and streaming the trace data out or buffering that trace data to be streamed out later. A particular constraint is that the amount of trace data generated can be disadvantageously large resulting in an increase in the on-chip memory requirements for buffering that trace data and/or an increase in the required provision for transmitting the trace data out of the chip, such as an increase in the number of pins that need to be dedicated to the trace functionality. In this context, measures which reduce the size of the trace data generated are strongly advantageous.
It is known to provide systems in which instruction trace data which provides an indication of whether a particular instruction executed is encoded in instruction trace words. This is done by encoding runs of sequential instructions executed terminated by a branch instruction. Thus, a particular instruction trace word may encode the detection of a run of four sequential instructions execution followed by a branch instruction.